1 data sheet acquired from harris semiconductor schs197e features typical propagation delay = 8ns at v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30%of v cc at v cc = 5v description the ?c4002 logic gate utilizes silicon gate cmos technology to achieve operating speeds similar to lsttl gates with the low power consumption of standard cmos integrated circuits. all devices have the ability to drive 10 lsttl loads. the ?c4002 logic family is functional as well as pin compatible with the standard ls logic family. pinout CD54HC4002 (cerdip) cd74hc4002 (pdip, soic, sop, tssop) top view ordering information part number temp. range ( o c) package CD54HC4002f3a -55 to 125 14 ld cerdip cd74hc4002e -55 to 125 14 ld pdip cd74hc4002m -55 to 125 14 ld soic cd74hc4002mt -55 to 125 14 ld soic cd74hc4002m96 -55 to 125 14 ld soic cd74hc4002nsr -55 to 125 14 ld sop cd74hc4002pw -55 to 125 14 ld tssop cd74hc4002pwr -55 to 125 14 ld tssop cd74hc4002pwt -55 to 125 14 ld tssop note: when ordering, use the entire part number. the suf?es 96 and r denote tape and reel. the suf? t denotes a small-quantity reel of 250. 1y 1a 1b 1c 1d nc gnd v cc 2y 2d 2c 2b 2a nc 1 2 3 4 5 6 7 14 13 12 11 10 9 8 august 1997 - revised october 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated CD54HC4002, cd74hc4002 high-speed cmos logic dual 4-input nor gate [ /title ( cd74h c 4002) / subject ( high s peed c mos l ogic d ual 4- i nput n or g ate)
2 functional diagram logic symbol truth table inputs output na nb nc nd ny llllh hxxxl xhxxl xxhxl xxxhl h = high voltage level, l = low voltage level, x = irrelevant 1a 1c 2a 2b 2d 2 4 5 9 11 12 1 2y 1y 13 1d gnd = 7 v cc = 14 nc = 6, 8 2c 1b 3 10 na nb ny nc nd CD54HC4002, cd74hc4002
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) package thermal impedance, ja (see note 1): e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 o c/w m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 o c/w ns (sop) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 o c/w pw (tssop) package . . . . . . . . . . . . . . . . . . . . . . . . . 113 o c/w maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 2 - 20 - 40 a CD54HC4002, cd74hc4002
4 switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units typ max max max hc types propagation delay, na, nb, nc, nd to ny t plh, t phl c l = 50pf 2 - 100 125 150 ns 4.5 - 20 25 30 ns 6 - 17 21 26 ns c l = 15pf 5 8 - - - ns output transition times (figure 1) t tlh , t thl c l = 50pf 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns input capacitance c in ---1010 10pf power dissipation capacitance (notes 2, 3) c pd c l = 15pf 5 22 - - - pf notes: 2. c pd is used to determine the dynamic power consumption, per gate. 3. p d = v cc 2 f i (c pd + c l ) where f i = input frequency, c l = output load capacitance, v cc = supply voltage. test circuit and waveform figure 1. hc and hcu transition times and propagation delay times, combination logic t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% CD54HC4002, cd74hc4002
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) CD54HC4002f3a active cdip j 14 1 tbd a42 snpb n / a for pkg type cd74hc4002e active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc4002ee4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc4002m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002mt active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002mte4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002nsr active so ns 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002nsre4 active so ns 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002pw active tssop pw 14 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002pwe4 active tssop pw 14 90 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002pwr active tssop pw 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002pwre4 active tssop pw 14 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002pwt active tssop pw 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc4002pwte4 active tssop pw 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) package option addendum www.ti.com 6-dec-2006 addendum-page 1
(3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 6-dec-2006 addendum-page 2
mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
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